The invention lies in the electronics and communications fields. Specifically, the invention relates to an apparatus for processing and generating data using a digital signal processor. The apparatus includes an interface unit allocated to a signal processor. The interface reads in and preprocesses the data to be processed and/or the data required for processing, and/or generates data and for the signal processor to pick up and/or picks up, postprocesses and outputs data which the signal processor processes or generates and supplies for pickup. The interface unit has a preprocessing and postprocessing device provided for pre- and postprocessing the data. A memory device is provided for supplying the data that have been preprocessed and are to be postprocessed for the signal processor or the preprocessing and postprocessing device to pick up. The preprocessing and postprocessing device has an expansion/compression device which can be used to expand the data read in and to compress the data to be output. The memory device is set up such that the preprocessing and postprocessing device and the signal processor can have quasi-simultaneous read and write access.
Such methods and apparatuses are used, by way of example but by no means exclusively, in ISDN private branch exchanges. ISDN private branch exchanges are systems, generally installed on a telecommunication subscriber""s premises, which can be used to connect a multiplicity of telecommunications terminals (telephones, fax machines, modems and the like) which are connected to them to one another and/or to one or more subscriber lines (exchange lines) in a telecommunications network.
Patent Abstracts of Japan Vol. 095, No. 002, Mar. 31, 1995 and JP 06 326870 A discloses an apparatus, for example, which has a dual port RAM for processing data interchanged between a modem and a fax more efficiently. With that configuration it is possible for the modem and the fax to write to and read from the dual port RAM at the same time. The modem has a signal processor, which processes the data, and a front-end processor connected upstream of the signal processor for preprocessing the data.
A conventional design of an ISDN private branch exchange is illustrated in FIG. 4. There, the private branch exchange includes one or more transceivers 11a, 11b, . . . 11n, a digital signal processor 12 and a control and switching device 13; the transceivers 11a, 11b, . . . 11n and the digital signal processor 12 are connected to the control and switching device 13 via connection lines 14.
The transceivers 11a, 11b, . . . 11n can have telecommunications terminals and/or one or more exchange lines connected to them. The number of transceivers 11a, 11b, . . . 11n to be provided is geared to the number and types of telecommunications terminals and exchange lines to be connected. In the exemplary embodiment under consideration, the transceiver 11a may be designed for connecting one or more conventional (analog) telecommunications terminals, the transceiver 11b may be designed for connecting one or more (digital) ISDN telecommunications terminals, and the transceiver 11n may be designed for connecting one or more ISDN exchange lines. In this context, the term xe2x80x9cdesignedxe2x80x9d is to be understood to mean constructed and configured.
Calls incoming via an exchange line from the telephone company are forwarded via the transceiver 11n to the control and switching device 13 and from there to the telecommunications terminal addressed by the call; outgoing calls from the telecommunications terminals are likewise routed to the control and switching device 13 and from there are connected to the specified location, which can be another of the telecommunications terminals connected to the private branch exchange or can be one of the connected exchange lines.
The control and switching device 13 supplies the signal processor 12 with all the data and information received by the private branch exchange from the telecommunications terminals and telephone company exchange lines. The signal processor 12 processes the received data as necessary to produce modified data, or generates new data and outputs or returns the data to the control and switching device 13. The control and switching device 13 receives the data and outputs them to the addressed telecommunications terminals and exchange lines in place of the data received by the telecommunications terminals and exchange lines.
This means that, to name just a few from an almost arbitrary number of examples, it is possible, among other things, to:
generate specific signal tones (call connected signal, busy signal) and/or specific messages (for example a message indicating that the call will not be connected because a telecommunications terminal with the service indicator xe2x80x9ctelephonexe2x80x9d is calling a telecommunications terminal with the service indicator xe2x80x9cfaxxe2x80x9d) and the like;
feed back the subscriber""s speech into the telephone muted on the telephone so that it can be overheard by the speaker; and
connect more than two subscribers and/or telecommunications terminals to one another (conference call connection).
However, experience shows that the tasks to be dealt with by the signal processor to achieve this take it to its performance limits very quickly. The result of this is that either a number of signal processors have to be used or certain convenience features of the private branch exchange have to be sacrificed. This is obviously a considerable disadvantage.
It is accordingly an object of the invention to provide an apparatus for processing and generating data with a digital signal processor, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables even work-intensive processing and generation of data using low-power and/or a minimal number of signal processors.
With the foregoing and other objects in view there is provided, in accordance with the invention, an apparatus for processing and generating data, comprising:
a digital signal processor;
an interface unit connected to the signal processor, the interface unit being adapted to read in and preprocess data for the signal processor and to postprocess and output data from the signal processor;
the interface unit including a preprocessing and post-processing device for preprocessing and postprocessing the data, and a memory device connected to the preprocessing and postprocessing device and to the signal processor;
the memory device being divided into four memory areas including two memory areas reserved for write access by the preprocessing and postprocessing device and for read access by the signal processor, and two memory areas reserved for write access by the signal processor and for read access by the preprocessing and postprocessing device.
The memory, therefore, allowing quasi-simultaneous read and write access by the preprocessing and postprocessing device and by the signal processor
In other words, an interface unit is provided which is allocated to the signal processor and reads in and preprocesses the data to be processed and/or data required for processing and/or generating data and supplies it for the signal processor to pick up and/or picks up, postprocesses and outputs data which the signal processor processes or generates and supplies for pickup. To this end, the interface unit has a pre- and postprocessing device provided for pre- and postprocessing the data, and a memory device provided for supplying the data which has been preprocessed and is to be postprocessed for the signal processor or the pre- and postprocessing device to pick up. The pre- and postprocessing device has an expansion/compression device which can be used to expand the data read in and to compress the data to be output. The memory device is designed such that the pre- and postprocessing device and the signal processor can have read and/or write access to it at virtually the same time. According to the invention, the memory device is divided into four memory areas, two of which are reserved for the pre- and postprocessing device to write to and for the signal processor to read from, and the other two are reserved for the signal processor to write to and for the pre- and postprocessing device to read from.
The input and/or output of data and its pre- and/or postprocessing by the interface unit associated with the signal processor relieve the burden on the signal processor quite significantly and thereby make it possible for the signal processor to be essentially able to provide its full performance for the actual data processing and/or data generation.
Hence, an apparatus has been found by means of which even work-intensive processing and generation of data is possible using low-power and/or a minimal number of signal processors.
At the same time, however, the interface unit relieving the burden on the signal processor can be of relatively simple design and relatively simple to operate, because its function can be limited to carrying out simple (yet in the aggregate very time-consuming) pre- and/or postprocessing steps, such as serial/parallel and parallel/serial conversions, table-supported coding or decoding operations, and the like.
In accordance with an added feature of the invention, the two memory areas reserved for write access by the preprocessing and postprocessing device and for read access by the signal processor include a first memory area reserved for write access and a second memory area reserved for read access, and the first and second memory areas are interchanged cyclically during operation.
In accordance with an additional feature of the invention, the two memory areas reserved for write access by the signal processor and for read access by the preprocessing and postprocessing device include a third memory area reserved for write access by the signal processor and a fourth memory area reserved for read access by the preprocessing and postprocessing device, and the third and fourth memory areas are interchanged cyclically during operation.
In accordance with another feature of the invention, the apparatus is an integral part of an ISDN switching system.
In accordance with a further feature of the invention, the memory areas of the memory device are dimensioned to store decompressed data in an IOM-2 frame.
In accordance with again an added feature of the invention, the preprocessing and postprocessing device includes a serial/parallel converter for converting serial input data to parallel data. Preferably, the preprocessing and post-processing device also includes a parallel/serial converter for converting parallel input data to serial data.
In accordance with a concomitant feature of the invention, the preprocessing and postprocessing device includes an expansion/compression device adapted to expand input data and to compress output data. In a preferred variant of the invention, the expansion/compression device expands and compresses data using tables stored in a read-only memory device.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an apparatus for processing and generating data using a digital signal processor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.